![]() ![]() ![]() Values Parameter Symbol Unit Note / Test Condition Min. For layout recommendations please use provided application notes or contact Infineon sales office. Stray inductances and coupling capacitances must be minimized. 650 - V Drain-source breakdown voltage Gate threshold voltage) V(BRDSS VIGS)th 3.5 4 4.5 V 1 Zero gate voltage drain current loss 100 ЦА Vos=0V, l=1mA Vos Vos, lo=0.82mA Vos=650V, Vos=0V, T=25☌ Vos=650V, VGS=OV, T=150☌ Vos=20V, Vos=0V Vos=10V, lp=16.4A, T=25☌ Vos=10V, lo=16.4A, T=150☌ F=250kHz, open drain Gate-source leakage current loss 0.1 ЦА Drain-source on-state resistance Rosion) 0.062 0.075 0.139 Ω Gate resistance Ro 5.8 Ω Table 5 Dynamic characteristics External parasitic elements (PCB layout) influence switching behavior significantly. Table 4 Static characteristics Values Parameter Symbol Unit Note / Test Condition Min. Table 2 Maximum ratings Parameter Symbol Unit Note / Test Condition Min. Table 1 Key Performance Parameters Parameter Value Unit Vos 650 IV Ros(on), max 75 m2 | Qg, typ 68 nC 139 A lo,pulse 8.8 UJ Eoss 400V Body diode dif/dt 1300 Alus ![]()
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